The invention relates to an electronic phase-locked loop (PLL) for jitter-attenuated clock multiplication, in particular as part of an integrated circuit (IC) for integrated services communications networks (ISDN), data communication or networks.
In the prior art, it is customary for the frequency to be set in such a way that it corresponds to a reference frequency. For this purpose, analog circuit arrangements have a controllable oscillator whose output signal is compared with the reference frequency in a phase detector. The output signal of the analog phase detector in turn sets the frequency of the controllable oscillator via a regulated system. An analog circuit arrangement of this type is generally more difficult to integrate than a digital circuit arrangement and usually requires additional components. The regulation is fairly accurate.
A digital implementation of a phase-locked loop is simple to integrate, affords the possibilities of rapid conversion to new technologies by using synthesis tools, and is relatively independent of fluctuations in the process for fabricating the integrated circuit (IC). The regulating accuracy can be achieved right down to the lowest discretization level for the digital representation of the numerical values.
One disadvantage of the digital PLL that has been customary heretofore is that, on account of inherent quantization, the PLL undergoes transition into a so-called xe2x80x9climit cyclexe2x80x9d and henceforth alternates between a phase error of +1, 0 and xe2x88x921; as a result, the high-frequency clock signal generated has a slow but unavoidable variance, called xe2x80x9cjitterxe2x80x9d.
In the publication relating to the conference xe2x80x9cIEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCExe2x80x9d, CH2584-1/88/0000-0051, pages 9.5.1 to 9.5.3, a description is given, by Rockwell International Semiconductor Products Division, i.e. by the authors Shi and al., of an electronic circuit arrangement designated xe2x80x9cJitter Attenuation Phase Locked Loop using switched capacitor controlled crystal oscillatorxe2x80x9d, which is intended to effect jitter attenuation.
A phase-locked loop (PLL) is used which attenuates jitter amplitudes of up to 30 unit intervals (UI) at a bandwidth of less than 2 Hz. The PLL has a crystal oscillator which is controlled in three frequencies by switched capacitors, and a down-counting sequential logic phase/frequency detector. By dynamic variation of the charging capacitance, the frequency of the oscillator is adjusted in accordance with the operating cycle of the control signal. Digital CMOS technology is used in this case. This technology does not require a complicated analog circuit. The digital control logic is simple.
DE-A1-39 20 008 describes an electronic phase-locked loop (PLL) appertaining to communications and data technology which has a phase comparator and an oscillator controlled by means of a switching matrix designed as capacitance or inductance matrix. The frequency of the oscillator can be set precisely, over the accuracy values that are limited by the tolerance limits of the switching matrix, by virtue of the fact that at least one switching element, preferably the least significant one, of the switching matrix is driven by a pulse length modulator. A first output signal burst formed by a microprocessor is fed to the switching matrix, and at least one further output signal burst is applied to the pulse length modulator. The pulse length modulator is clocked by a clock signal derived from an output signal of the voltage-controlled oscillator, said clock signal also driving a switch for driving the switching element.
Consequently, just like in the PLL according to the IEEE Conference publication discussed above, what is present is digital, in this case additionally refined, stepwise control of the oscillator which, moreover, certainly helps to reduce the so-called jitter, even though such xe2x80x9cJitterxe2x80x9d is not mentioned per se.
Against the background of this prior art, the invention is based on the object of attenuating, in an electronic co phase-locked loop (PLL) of digital design, even the jitter of the lowest digital discretization level.
The invention provides a digital phase-locked loopxe2x80x94which can be synthesized from standard cellsxe2x80x94with the assistance of an analog phase detector and a circuit for lock detection, whereby the disadvantages hitherto of the purely digital solution are overcome.
The invention is explained in more detail below in an exemplary embodiment and with reference to the drawings.